feat: Intel/AMD AVX & MSR sensors, Gigabit PCIe NICs, AHCI SATA, FAT32, and ogit in Ring 3
This commit is contained in:
RarDog
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#pragma once
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#include "stdint.h"
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#include "stdbool.h"
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#include "stddef.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SATA_SIG_ATA 0x00000101 // SATA drive
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#define SATA_SIG_ATAPI 0xEB140101 // SATAPI drive
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#define SATA_SIG_SEMB 0xC33C0101 // Enclosure management bridge
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#define SATA_SIG_PM 0x96690101 // Port multiplier
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#define AHCI_DEV_NULL 0
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#define AHCI_DEV_SATA 1
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#define AHCI_DEV_SEMB 2
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#define AHCI_DEV_PM 3
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#define AHCI_DEV_SATAPI 4
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#define HBA_PORT_IPM_ACTIVE 1
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#define HBA_PORT_DET_PRESENT 3
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// Register FIS - Host to Device
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#define FIS_TYPE_REG_H2D 0x27
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#define ATA_CMD_READ_DMA_EXT 0x25
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#define ATA_CMD_WRITE_DMA_EXT 0x35
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typedef volatile struct tagHBA_PORT {
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uint32_t clb; // 0x00, Command list base address, 1K-byte aligned
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uint32_t clbu; // 0x04, Command list base address upper 32 bits
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uint32_t fb; // 0x08, FIS base address, 256-byte aligned
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uint32_t fbu; // 0x0C, FIS base address upper 32 bits
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uint32_t is; // 0x10, Interrupt status
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uint32_t ie; // 0x14, Interrupt enable
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uint32_t cmd; // 0x18, Command and status
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uint32_t rsv0; // 0x1C, Reserved
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uint32_t tfd; // 0x20, Task file data
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uint32_t sig; // 0x24, Signature
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uint32_t ssts; // 0x28, SATA status (SCR0:SStatus)
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uint32_t sctl; // 0x2C, SATA control (SCR2:SControl)
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uint32_t serr; // 0x30, SATA error (SCR1:SError)
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uint32_t sact; // 0x34, SATA active (SCR3:SActive)
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uint32_t ci; // 0x38, Command issue
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uint32_t sntf; // 0x3C, SATA notification (SCR4:SNotification)
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uint32_t fbs; // 0x40, FIS-based switch control
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uint32_t rsv1[11]; // 0x44 ~ 0x6F, Reserved
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uint32_t vendor[4]; // 0x70 ~ 0x7F, vendor specific
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} HBA_PORT;
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typedef volatile struct tagHBA_MEM {
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uint32_t cap; // 0x00 - 0x03, Host capability
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uint32_t ghc; // 0x04 - 0x07, Global host control
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uint32_t is; // 0x08 - 0x0B, Interrupt status
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uint32_t pi; // 0x0C - 0x0F, Port implemented
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uint32_t vs; // 0x10 - 0x13, Version
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uint32_t ccc_ctl; // 0x14 - 0x17, Command completion coalescing control
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uint32_t ccc_pts; // 0x18 - 0x1B, Command completion coalescing ports
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uint32_t em_loc; // 0x1C - 0x1F, Enclosure management location
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uint32_t em_ctl; // 0x20 - 0x23, Enclosure management control
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uint32_t cap2; // 0x24 - 0x27, Host capabilities extended
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uint32_t bohc; // 0x28 - 0x2B, BIOS/OS handoff control and status
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uint8_t rsv[0xA0-0x2C];
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uint8_t vendor[0x100-0xA0];
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HBA_PORT ports[32]; // 0x100 ~ 0x10FF, Port control registers
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} HBA_MEM;
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typedef struct tagHBA_CMD_HEADER {
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uint8_t cfl:5; // Command FIS length in DWORDS, 2 ~ 16
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uint8_t a:1; // ATAPI
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uint8_t w:1; // Write, 1: H2D, 0: D2H
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uint8_t p:1; // Prefetchable
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uint8_t r:1; // Reset
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uint8_t b:1; // BIST
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uint8_t c:1; // Clear busy upon R_OK
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uint8_t rsv0:1; // Reserved
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uint8_t pmp:4; // Port multiplier port
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uint16_t prdtl; // Physical region descriptor table length in entries
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volatile uint32_t prdbc; // Physical region descriptor byte count transferred
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uint32_t ctba; // Command table descriptor base address
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uint32_t ctbau; // Command table descriptor base address upper 32 bits
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uint32_t rsv1[4]; // Reserved
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} HBA_CMD_HEADER;
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typedef struct tagHBA_PRDT_ENTRY {
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uint32_t dba; // Data base address
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uint32_t dbau; // Data base address upper 32 bits
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uint32_t rsv0; // Reserved
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uint32_t dbc:22; // Byte count, 4M max
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uint32_t rsv1:9; // Reserved
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uint32_t i:1; // Interrupt on completion
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} HBA_PRDT_ENTRY;
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typedef struct tagHBA_CMD_TABLE {
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uint8_t cfis[64]; // Command FIS
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uint8_t acmd[16]; // ATAPI command, 12 or 16 bytes
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uint8_t rsv[48]; // Reserved
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HBA_PRDT_ENTRY prdt_entry[1]; // Physical region descriptor table entries, 0 ~ 65535
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} HBA_CMD_TABLE;
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typedef struct tagFIS_REG_H2D {
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uint8_t fis_type; // FIS_TYPE_REG_H2D
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uint8_t pmport:4; // Port multiplier
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uint8_t rsv0:3; // Reserved
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uint8_t c:1; // 1: Command, 0: Control
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uint8_t command; // Command register
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uint8_t featurel; // Feature register, 7:0
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uint8_t lba0; // LBA low register, 7:0
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uint8_t lba1; // LBA mid register, 15:8
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uint8_t lba2; // LBA high register, 23:16
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uint8_t device; // Device register
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uint8_t lba3; // LBA register, 31:24
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uint8_t lba4; // LBA register, 39:32
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uint8_t lba5; // LBA register, 47:40
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uint8_t featureh; // Feature register, 15:8
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uint8_t countl; // Count register, 7:0
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uint8_t counth; // Count register, 15:8
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uint8_t icc; // Isochronous command completion
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uint8_t control; // Control register
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uint8_t rsv1[4]; // Reserved
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} FIS_REG_H2D;
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typedef struct ahci_device {
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uint8_t bus;
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uint8_t slot;
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uint8_t func;
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uint64_t abar_phys;
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HBA_MEM *hba_mem;
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int active_port;
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bool initialized;
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uint64_t sector_count;
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} ahci_device_t;
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extern ahci_device_t g_ahci;
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int ahci_detect_and_init(void);
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int ahci_read_sectors(uint64_t lba, uint32_t count, void *buf);
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int ahci_write_sectors(uint64_t lba, uint32_t count, const void *buf);
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,107 @@
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#pragma once
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#include "stdint.h"
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#include "stdbool.h"
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#include "stddef.h"
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#include "pci.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define E1000_NUM_RX_DESC 16
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#define E1000_NUM_TX_DESC 16
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#define E1000_RX_BUF_SIZE 2048
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#define E1000_TX_BUF_SIZE 2048
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// E1000 MMIO Register Offsets
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#define E1000_REG_CTRL 0x0000
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#define E1000_REG_STATUS 0x0008
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#define E1000_REG_EEPROM 0x0014
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#define E1000_REG_ICR 0x00C0
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#define E1000_REG_IMS 0x00D0
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#define E1000_REG_RCTL 0x0100
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#define E1000_REG_RDBAL 0x2800
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#define E1000_REG_RDBAH 0x2804
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#define E1000_REG_RDLEN 0x2808
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#define E1000_REG_RDH 0x2810
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#define E1000_REG_RDT 0x2818
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#define E1000_REG_TCTL 0x0400
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#define E1000_REG_TDBAL 0x3800
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#define E1000_REG_TDBAH 0x3804
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#define E1000_REG_TDLEN 0x3808
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#define E1000_REG_TDH 0x3810
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#define E1000_REG_TDT 0x3818
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#define E1000_REG_RAL 0x5400
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#define E1000_REG_RAH 0x5404
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// RCTL bits
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#define E1000_RCTL_EN (1 << 1)
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#define E1000_RCTL_SBP (1 << 2)
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#define E1000_RCTL_UPE (1 << 3)
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#define E1000_RCTL_MPE (1 << 4)
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#define E1000_RCTL_BAM (1 << 15)
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#define E1000_RCTL_BSIZE_2K (0 << 16)
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#define E1000_RCTL_SECRC (1 << 26)
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// TCTL bits
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#define E1000_TCTL_EN (1 << 1)
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#define E1000_TCTL_PSP (1 << 3)
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#define E1000_TCTL_CT_SHIFT 4
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#define E1000_TCTL_COLD_SHIFT 12
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// TX Command bits
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#define E1000_TXD_CMD_EOP (1 << 0)
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#define E1000_TXD_CMD_IFCS (1 << 1)
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#define E1000_TXD_CMD_RS (1 << 3)
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// RX Status bits
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#define E1000_RXD_STAT_DD (1 << 0)
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#define E1000_RXD_STAT_EOP (1 << 1)
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// E1000 RX Descriptor
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typedef struct __attribute__((packed)) e1000_rx_desc {
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uint64_t addr;
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uint16_t length;
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uint16_t checksum;
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uint8_t status;
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uint8_t errors;
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uint16_t special;
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} e1000_rx_desc_t;
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// E1000 TX Descriptor
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typedef struct __attribute__((packed)) e1000_tx_desc {
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uint64_t addr;
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uint16_t length;
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uint8_t cso;
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uint8_t cmd;
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uint8_t status;
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uint8_t css;
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uint16_t special;
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} e1000_tx_desc_t;
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typedef struct e1000_device {
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uint8_t bus;
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uint8_t slot;
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uint8_t func;
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uint16_t device_id;
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uint64_t mmio_base;
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uint8_t mac[6];
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uint32_t rx_cur;
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uint32_t tx_cur;
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uint64_t rx_packets;
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uint64_t rx_bytes;
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uint64_t tx_packets;
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uint64_t tx_bytes;
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bool initialized;
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} e1000_device_t;
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extern e1000_device_t g_e1000;
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int e1000_detect_and_init(void);
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int e1000_send_packet(const void *packet, size_t length);
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int e1000_receive_packet(void *buffer, size_t max_length);
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,75 @@
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#pragma once
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#include "stdint.h"
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#include "stdbool.h"
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#include "stddef.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct __attribute__((packed)) fat32_bpb {
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uint8_t jmp[3];
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char oem[8];
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uint16_t bytes_per_sector;
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uint8_t sectors_per_cluster;
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uint16_t reserved_sectors;
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uint8_t num_fats;
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uint16_t root_entry_count;
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uint16_t total_sectors_16;
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uint8_t media_type;
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uint16_t fat_size_16;
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uint16_t sectors_per_track;
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uint16_t num_heads;
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uint32_t hidden_sectors;
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uint32_t total_sectors_32;
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uint32_t fat_size_32;
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uint16_t ext_flags;
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uint16_t fs_version;
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uint32_t root_cluster;
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uint16_t fs_info;
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uint16_t backup_boot_sector;
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uint8_t reserved[12];
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uint8_t drive_number;
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uint8_t reserved1;
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uint8_t boot_signature;
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uint32_t volume_id;
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char volume_label[11];
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char fs_type[8];
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} fat32_bpb_t;
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typedef struct __attribute__((packed)) fat32_dir_entry {
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char name[11];
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uint8_t attr;
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uint8_t nt_reserved;
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uint8_t creation_time_tenth;
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uint16_t creation_time;
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uint16_t creation_date;
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uint16_t last_access_date;
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uint16_t first_cluster_high;
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uint16_t write_time;
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uint16_t write_date;
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uint16_t first_cluster_low;
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uint32_t file_size;
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} fat32_dir_entry_t;
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typedef struct fat32_fs {
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uint32_t partition_lba;
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uint32_t fat_start_lba;
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uint32_t cluster_start_lba;
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uint32_t sectors_per_cluster;
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uint32_t bytes_per_cluster;
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uint32_t root_cluster;
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bool mounted;
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} fat32_fs_t;
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extern fat32_fs_t g_fat32;
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int fat32_mount(void);
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int fat32_list(const char *dir_path, char *out_buf, size_t buf_size);
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int fat32_read_file(const char *path, void *buffer, size_t max_len);
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int fat32_write_file(const char *path, const void *buffer, size_t len);
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,34 @@
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#pragma once
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#include "stdint.h"
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#include "stdbool.h"
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#include "stddef.h"
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#include "pci.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct r8169_device {
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uint8_t bus;
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uint8_t slot;
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uint8_t func;
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uint16_t device_id;
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uint16_t io_base;
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uint8_t mac[6];
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uint64_t rx_packets;
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uint64_t rx_bytes;
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uint64_t tx_packets;
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uint64_t tx_bytes;
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bool initialized;
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} r8169_device_t;
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extern r8169_device_t g_r8169;
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int r8169_detect_and_init(void);
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int r8169_send_packet(const void *packet, size_t length);
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int r8169_receive_packet(void *buffer, size_t max_length);
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#ifdef __cplusplus
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}
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#endif
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