feat(sched): implement preemptive time-slicing multitasking via PIT 8254 timer ISR (Vector 32)

2026-09-02 16:54:19 +03:00
parent 448b0e710e
commit e7a0d2e6b1
6 changed files with 248 additions and 74 deletions
@@ -0,0 +1,49 @@
+/* opencoreC - Timer Preemptive Interrupt Trampoline (Vector 32 / 0x20) */
+.global timer_isr_entry
+.extern timer_interrupt_handler
+
+.section .text
+timer_isr_entry:
+    /* 1. Save all general-purpose registers to form a complete interrupt context frame */
+    push rax
+    push rbx
+    push rcx
+    push rdx
+    push rsi
+    push rdi
+    push rbp
+    push r8
+    push r9
+    push r10
+    push r11
+    push r12
+    push r13
+    push r14
+    push r15
+
+    /* 2. Pass current saved stack pointer in RDI */
+    mov rdi, rsp
+    call timer_interrupt_handler
+
+    /* 3. Switch stack pointer to returned value (RAX contains next thread's RSP) */
+    mov rsp, rax
+
+    /* 4. Restore all general-purpose registers */
+    pop r15
+    pop r14
+    pop r13
+    pop r12
+    pop r11
+    pop r10
+    pop r9
+    pop r8
+    pop rbp
+    pop rdi
+    pop rsi
+    pop rdx
+    pop rcx
+    pop rbx
+    pop rax
+
+    /* 5. Return from interrupt (IRETQ restores RIP, CS, RFLAGS, RSP, SS) */
+    iretq