RarDog
eed05c1eca
- Implement Limine v8 boot protocol requests in dedicated PT_LOAD RW segment - Configure IOPL=3 and SSE in arch setup for Ring 3 drivers and libc - Unify scheduler context switching via switch_to and preempt_tick - Support dual-source keyboard/serial input in sys_key_read - Add automated 'make image' and 'make run' targets for instant QEMU launch - Complete interactive UNIX-like shell (osh) with built-in commands & ramdisk
218 lines
7.6 KiB
Rust
218 lines
7.6 KiB
Rust
//! Interrupt Descriptor Table (IDT) and Exception Handling
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use crate::kprintln;
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use crate::sched::SCHEDULER;
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use crate::drivers::timer::send_eoi;
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use core::mem::size_of;
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#[repr(C, packed)]
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#[derive(Clone, Copy)]
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pub struct IdtEntry {
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offset_low: u16,
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selector: u16,
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ist: u8,
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type_attr: u8,
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offset_mid: u16,
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offset_high: u32,
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_reserved: u32,
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}
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impl IdtEntry {
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pub const fn missing() -> Self {
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Self {
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offset_low: 0,
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selector: 0,
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ist: 0,
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type_attr: 0,
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offset_mid: 0,
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offset_high: 0,
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_reserved: 0,
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}
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}
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pub fn set_handler(&mut self, handler: u64, ist: u8, dpl: u8) {
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self.offset_low = (handler & 0xffff) as u16;
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self.selector = 0x08; // Kernel code segment
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self.ist = ist & 0x7;
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self.type_attr = 0x80 | ((dpl & 0x3) << 5) | 0x0E; // 64-bit Interrupt Gate Present
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self.offset_mid = ((handler >> 16) & 0xffff) as u16;
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self.offset_high = ((handler >> 32) & 0xffffffff) as u32;
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self._reserved = 0;
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}
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}
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#[repr(C, packed)]
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struct IdtDescriptor {
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limit: u16,
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base: u64,
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}
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static mut IDT: [IdtEntry; 256] = [IdtEntry::missing(); 256];
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extern "C" {
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fn default_isr_stub();
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fn timer_isr_entry();
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fn keyboard_isr_entry();
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}
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// Global assembly ISR stub with vector ID pushed as separate stubs (0-31)
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core::arch::global_asm!(
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// With error code: CPU already pushed error_code, we push vector on top
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".macro ISR_ERR_CODE num",
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"isr_stub_\\num:",
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"push \\num", // push vector number (error_code already on stack below)
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"jmp default_isr_common",
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".endm",
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// Without error code: push dummy 0, then vector
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".macro ISR_NO_ERR num",
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"isr_stub_\\num:",
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"push 0", // dummy error_code
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"push \\num", // push vector number
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"jmp default_isr_common",
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".endm",
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"ISR_NO_ERR 0", "ISR_NO_ERR 1", "ISR_NO_ERR 2", "ISR_NO_ERR 3",
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"ISR_NO_ERR 4", "ISR_NO_ERR 5", "ISR_NO_ERR 6", "ISR_NO_ERR 7",
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"ISR_ERR_CODE 8","ISR_NO_ERR 9", "ISR_ERR_CODE 10","ISR_ERR_CODE 11",
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"ISR_ERR_CODE 12","ISR_ERR_CODE 13","ISR_ERR_CODE 14","ISR_NO_ERR 15",
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"ISR_NO_ERR 16","ISR_ERR_CODE 17","ISR_NO_ERR 18","ISR_NO_ERR 19",
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"ISR_NO_ERR 20","ISR_ERR_CODE 21","ISR_NO_ERR 22","ISR_NO_ERR 23",
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"ISR_NO_ERR 24","ISR_NO_ERR 25","ISR_NO_ERR 26","ISR_NO_ERR 27",
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"ISR_NO_ERR 28","ISR_NO_ERR 29","ISR_ERR_CODE 30","ISR_NO_ERR 31",
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".global default_isr_stub",
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"default_isr_stub:",
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"push 0", // dummy error code
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"push 255", // dummy vector
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"jmp default_isr_common",
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".global default_isr_common",
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"default_isr_common:",
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// Stack at this point (top to bottom):
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// RSP+0: vector
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// RSP+8: error_code
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// RSP+16: RIP (pushed by CPU)
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// RSP+24: CS
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// RSP+32: RFLAGS
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// RSP+40: RSP (if ring change)
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// RSP+48: SS (if ring change)
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"push rax", "push rcx", "push rdx",
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"push rsi", "push rdi",
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"push r8", "push r9", "push r10", "push r11",
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"mov rdi, rsp",
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"call raw_exception_handler",
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"pop r11", "pop r10", "pop r9", "pop r8",
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"pop rdi", "pop rsi",
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"pop rdx", "pop rcx", "pop rax",
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// skip vector + error_code from stack
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"add rsp, 16",
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"iretq"
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);
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pub unsafe fn init() {
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let idt_ptr = core::ptr::addr_of_mut!(IDT) as *mut IdtEntry;
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// Install per-vector stubs for exceptions 0-31
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extern "C" {
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fn isr_stub_0(); fn isr_stub_1(); fn isr_stub_2(); fn isr_stub_3();
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fn isr_stub_4(); fn isr_stub_5(); fn isr_stub_6(); fn isr_stub_7();
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fn isr_stub_8(); fn isr_stub_9(); fn isr_stub_10(); fn isr_stub_11();
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fn isr_stub_12(); fn isr_stub_13(); fn isr_stub_14(); fn isr_stub_15();
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fn isr_stub_16(); fn isr_stub_17(); fn isr_stub_18(); fn isr_stub_19();
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fn isr_stub_20(); fn isr_stub_21(); fn isr_stub_22(); fn isr_stub_23();
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fn isr_stub_24(); fn isr_stub_25(); fn isr_stub_26(); fn isr_stub_27();
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fn isr_stub_28(); fn isr_stub_29(); fn isr_stub_30(); fn isr_stub_31();
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}
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let exception_stubs: [u64; 32] = [
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isr_stub_0 as u64, isr_stub_1 as u64, isr_stub_2 as u64, isr_stub_3 as u64,
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isr_stub_4 as u64, isr_stub_5 as u64, isr_stub_6 as u64, isr_stub_7 as u64,
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isr_stub_8 as u64, isr_stub_9 as u64, isr_stub_10 as u64, isr_stub_11 as u64,
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isr_stub_12 as u64, isr_stub_13 as u64, isr_stub_14 as u64, isr_stub_15 as u64,
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isr_stub_16 as u64, isr_stub_17 as u64, isr_stub_18 as u64, isr_stub_19 as u64,
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isr_stub_20 as u64, isr_stub_21 as u64, isr_stub_22 as u64, isr_stub_23 as u64,
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isr_stub_24 as u64, isr_stub_25 as u64, isr_stub_26 as u64, isr_stub_27 as u64,
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isr_stub_28 as u64, isr_stub_29 as u64, isr_stub_30 as u64, isr_stub_31 as u64,
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];
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for (i, &stub_addr) in exception_stubs.iter().enumerate() {
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(*idt_ptr.add(i)).set_handler(stub_addr, 0, 0);
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}
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// Fill 32..255 with default stub
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let stub_addr = default_isr_stub as *const () as usize as u64;
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for i in 32..256usize {
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(*idt_ptr.add(i)).set_handler(stub_addr, 0, 0);
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}
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// Set Timer Interrupt (Vector 32 / 0x20)
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let timer_addr = timer_isr_entry as *const () as usize as u64;
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(*idt_ptr.add(32)).set_handler(timer_addr, 0, 0);
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// Set Keyboard Interrupt (Vector 33 / 0x21)
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let kbd_addr = keyboard_isr_entry as *const () as usize as u64;
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(*idt_ptr.add(33)).set_handler(kbd_addr, 0, 0);
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let descriptor = IdtDescriptor {
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limit: (size_of::<[IdtEntry; 256]>() - 1) as u16,
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base: idt_ptr as u64,
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};
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core::arch::asm!("lidt [{0}]", in(reg) &descriptor, options(preserves_flags));
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}
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#[repr(C)]
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pub struct ExceptionFrame {
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// Stack layout when raw_exception_handler is called (low addr = top of stack):
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// Pushed by default_isr_common: r11,r10,r9,r8,rdi,rsi,rdx,rcx,rax (in that push order)
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pub r11: u64, pub r10: u64, pub r9: u64, pub r8: u64,
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pub rdi: u64, pub rsi: u64, pub rdx: u64, pub rcx: u64, pub rax: u64,
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// Pushed by per-vector stub (in push order: vector first on top)
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pub vector: u64,
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pub error_code: u64,
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// Pushed by CPU hardware:
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pub rip: u64,
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pub cs: u64,
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pub rflags: u64,
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pub user_rsp: u64, // only present on ring transition
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pub ss: u64,
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}
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#[no_mangle]
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pub extern "C" fn raw_exception_handler(frame: *const ExceptionFrame) {
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unsafe {
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let v = (*frame).vector;
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let ec = (*frame).error_code;
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let rip = (*frame).rip;
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let cs = (*frame).cs;
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let rflags = (*frame).rflags;
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let names = [
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"#DE", "#DB", "NMI", "#BP", "#OF", "#BR", "#UD", "#NM",
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"#DF", "CSO", "#TS", "#NP", "#SS", "#GP", "#PF", "RES",
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"#MF", "#AC", "#MC", "#XM", "#VE", "#CP", "??" , "??" ,
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"??" , "??" , "??" , "??" , "??" , "??" , "#SX", "??" ,
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];
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let name = if v < 32 { names[v as usize] } else { "IRQ" };
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kprintln!("\n[EXCEPTION] Vec={} ({}) ErrCode={:#x} RIP={:#018x} CS={:#x} RFLAGS={:#x}",
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v, name, ec, rip, cs, rflags);
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if v == 14 {
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let cr2: u64;
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core::arch::asm!("mov {}, cr2", out(reg) cr2, options(nostack, preserves_flags));
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kprintln!(" #PF CR2 (faulting address): {:#018x}", cr2);
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}
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if v < 32 {
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kprintln!(" [HALT] Unrecoverable exception - CPU halted.");
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loop { core::arch::asm!("cli; hlt", options(nostack, preserves_flags)); }
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}
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}
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}
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#[no_mangle]
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pub extern "C" fn timer_interrupt_handler() {
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unsafe {
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send_eoi();
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let sched = &mut *core::ptr::addr_of_mut!(SCHEDULER);
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sched.preempt_tick();
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}
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}
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