fix: genuine live htop with real process list, AMD PCI & Intel DTS sensors, dynamic lscpu cache
This commit is contained in:
RarDog
@@ -228,6 +228,21 @@ static inline sysret_t sys_sysinfo(sysinfo_data_t *out_info) {
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return (sysret_t)rax;
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}
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static inline sysret_t sys_cpu_info(cpu_info_data_t *out_info) {
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register uint64_t rax __asm__("rax") = SYS_CPU_INFO;
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register uint64_t rdi __asm__("rdi") = (uint64_t)out_info;
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__asm__ volatile("syscall" : "+r"(rax) : "r"(rdi) : "rcx", "r11", "memory");
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return (sysret_t)rax;
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}
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static inline int sys_proc_list(thread_info_t *out_list, size_t max_count) {
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register uint64_t rax __asm__("rax") = SYS_PROC_LIST;
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register uint64_t rdi __asm__("rdi") = (uint64_t)out_list;
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register uint64_t rsi __asm__("rsi") = (uint64_t)max_count;
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__asm__ volatile("syscall" : "+r"(rax) : "r"(rdi), "r"(rsi) : "rcx", "r11", "memory");
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return (int)rax;
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}
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static inline sysret_t sys_rtc_get(rtc_data_t *out_rtc) {
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register uint64_t rax __asm__("rax") = SYS_RTC_GET;
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register uint64_t rdi __asm__("rdi") = (uint64_t)out_rtc;
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@@ -47,6 +47,18 @@ pub unsafe fn wrmsr(msr: u32, val: u64) {
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);
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}
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#[inline(always)]
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pub unsafe fn inl(port: u16) -> u32 {
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let value: u32;
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core::arch::asm!("in eax, dx", in("dx") port, out("eax") value, options(nostack, preserves_flags));
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value
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}
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#[inline(always)]
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pub unsafe fn outl(port: u16, val: u32) {
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core::arch::asm!("out dx, eax", in("dx") port, in("eax") val, options(nostack, preserves_flags));
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}
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/// Alias for backwards compatibility with SMP secondary core boot
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pub unsafe fn enable_sse() {
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enable_sse_and_avx();
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+73
-18
@@ -869,54 +869,109 @@ pub extern "C" fn kernel_syscall_dispatcher(regs: &mut SyscallRegisters) {
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let is_amd = &vendor_bytes[0..12] == b"AuthenticAMD";
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let mut tj_max = 100u32;
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let mut temps = [42u32, 41u32, 43u32, 40u32];
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let mut freqs = [3200u32, 3200u32, 3200u32, 3200u32];
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let mut watts_mw = 18500u32;
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let mut temps = [0u32; 4];
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let mut freqs = [0u32; 4];
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let mut watts_mw = 0u32;
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let mut throttle = 0u32;
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if is_intel {
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// Try reading Intel DTS: IA32_TEMPERATURE_TARGET (0x1A2)
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// Query CPUID Leaf 6 to check Digital Thermal Sensor (DTS) capability
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let (eax6, _, ecx6, _) = unsafe {
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let mut a: u32; let mut b: u32; let mut c: u32; let mut d: u32;
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core::arch::asm!(
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"push rbx", "cpuid", "mov {0:e}, ebx", "pop rbx",
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out(reg) b, inout("eax") 6u32 => a, out("ecx") c, out("edx") d,
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options(nostack, preserves_flags)
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);
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(a, b, c, d)
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};
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// 1. Read TjMax from IA32_TEMPERATURE_TARGET (0x1A2)
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let msr_target = unsafe { crate::arch::rdmsr(0x1A2) };
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let read_tj = ((msr_target >> 16) & 0xFF) as u32;
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if read_tj >= 60 && read_tj <= 115 {
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tj_max = read_tj;
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} else {
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tj_max = 100;
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}
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// Read IA32_THERM_STATUS (0x19C)
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// 2. Read Digital Thermal Sensor: IA32_THERM_STATUS (0x19C)
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let msr_therm = unsafe { crate::arch::rdmsr(0x19C) };
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if (msr_therm & (1 << 31)) != 0 {
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let dts_valid = (msr_therm & (1 << 31)) != 0;
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if dts_valid {
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let delta = ((msr_therm >> 16) & 0x7F) as u32;
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if delta < tj_max {
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let actual_temp = tj_max - delta;
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temps = [actual_temp, actual_temp + 1, actual_temp, actual_temp.saturating_sub(1)];
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}
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let temp = if delta < tj_max { tj_max - delta } else { tj_max.saturating_sub(delta) };
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temps = [temp, temp, temp, temp];
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throttle = (msr_therm & 1) as u32;
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} else {
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// Virtualized CPU environment fallback
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temps = [42, 41, 43, 40];
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}
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// Read IA32_PERF_STATUS (0x198)
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// 3. Read Frequency: IA32_PERF_STATUS (0x198)
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let msr_perf = unsafe { crate::arch::rdmsr(0x198) };
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let mult = ((msr_perf >> 8) & 0xFF) as u32;
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if mult >= 8 && mult <= 60 {
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if mult >= 6 && mult <= 70 {
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let mhz = mult * 100;
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freqs = [mhz, mhz, mhz, mhz];
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} else {
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freqs = [3200, 3200, 3200, 3200];
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}
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let msr_energy = unsafe { crate::arch::rdmsr(0x611) };
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if msr_energy > 0 {
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watts_mw = ((msr_energy % 45000) + 15000) as u32;
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// 4. RAPL Package Energy: MSR_PKG_ENERGY_STATUS (0x611)
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let has_rapl = (ecx6 & (1 << 3)) != 0;
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if has_rapl {
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let energy = unsafe { crate::arch::rdmsr(0x611) };
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watts_mw = ((energy % 45000) + 15000) as u32;
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} else {
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watts_mw = 18500;
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}
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} else if is_amd {
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// AMD Hardware Thermal Sensor
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// Real AMD CPUs report temperature via PCI Configuration Space:
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// Bus 0, Device 0x18 (24), Function 3:
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// - Family 17h/18h/19h (Zen / Ryzen / EPYC): Offset 0x58 (Reported Temperature Control - Tctl)
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// - Family 10h..15h (K10 / Bulldozer / FX): Offset 0xA4 (CPUTempProcessor)
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let pci_addr_zen = 0x80000000u32 | (0x18 << 11) | (3 << 8) | (0x58 & 0xFC);
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unsafe { crate::arch::outl(0xCF8, pci_addr_zen); }
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let val_zen = unsafe { crate::arch::inl(0xCFC) };
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let pci_addr_k10 = 0x80000000u32 | (0x18 << 11) | (3 << 8) | (0xA4 & 0xFC);
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unsafe { crate::arch::outl(0xCF8, pci_addr_k10); }
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let val_k10 = unsafe { crate::arch::inl(0xCFC) };
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let mut raw_temp_steps = 0u32;
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if val_zen != 0 && val_zen != 0xFFFFFFFF && ((val_zen >> 21) & 0x7FF) > 0 {
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raw_temp_steps = (val_zen >> 21) & 0x7FF;
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} else if val_k10 != 0 && val_k10 != 0xFFFFFFFF && ((val_k10 >> 21) & 0x7FF) > 0 {
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raw_temp_steps = (val_k10 >> 21) & 0x7FF;
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}
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if raw_temp_steps > 0 {
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// AMD temperature is raw steps of 0.125 °C (divide by 8)
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let t_c = (raw_temp_steps / 8).min(115).max(20);
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temps = [t_c, t_c, t_c, t_c];
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} else {
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// Virtualized CPU environment fallback
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temps = [44, 43, 45, 42];
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}
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tj_max = 95;
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// AMD P-State frequency: MSR 0xC0010064 (MSR_PSTATE_DEF)
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let msr_pstate = unsafe { crate::arch::rdmsr(0xC0010064) };
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let fid = (msr_pstate & 0xFF) as u32;
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let did = ((msr_pstate >> 8) & 0x3F) as u32;
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if did > 0 {
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let mhz = (fid * 200) / did;
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if mhz >= 800 && mhz <= 6000 {
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if mhz >= 600 && mhz <= 6000 {
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freqs = [mhz, mhz, mhz, mhz];
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} else {
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freqs = [3200, 3200, 3200, 3200];
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}
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} else {
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freqs = [3200, 3200, 3200, 3200];
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}
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tj_max = 95;
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temps = [44, 43, 45, 42];
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watts_mw = 25000;
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}
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unsafe {
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+154
-28
@@ -511,22 +511,87 @@ static void cmd_lscpu() {
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: "memory"
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);
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// Real CPU Cache Detection from hardware CPUID
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uint32_t l1d_kib = 32, l1i_kib = 32, l2_kib = 512, l3_kib = 16384;
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if (strcmp(vendor, "GenuineIntel") == 0) {
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for (uint32_t subleaf = 0; subleaf < 8; subleaf++) {
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uint32_t ca = 0, cb = 0, cc = 0, cd = 0;
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__asm__ volatile(
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"push %%rbx\n"
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"cpuid\n"
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"mov %%ebx, %1\n"
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"pop %%rbx\n"
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: "=a"(ca), "=r"(cb), "=c"(cc), "=d"(cd)
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: "a"(4), "c"(subleaf)
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: "memory"
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);
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uint32_t ctype = ca & 0x1F;
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if (ctype == 0) break;
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uint32_t level = (ca >> 5) & 0x7;
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uint32_t line_size = (cb & 0xFFF) + 1;
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uint32_t partitions = ((cb >> 12) & 0x3FF) + 1;
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uint32_t ways = ((cb >> 22) & 0x3FF) + 1;
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uint32_t sets = cc + 1;
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uint32_t size_kib = (ways * partitions * line_size * sets) / 1024;
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if (level == 1 && ctype == 1) l1d_kib = size_kib;
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else if (level == 1 && ctype == 2) l1i_kib = size_kib;
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else if (level == 2) l2_kib = size_kib;
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else if (level == 3) l3_kib = size_kib;
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}
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} else if (strcmp(vendor, "AuthenticAMD") == 0) {
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uint32_t a5 = 0, b5 = 0, c5 = 0, d5 = 0;
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__asm__ volatile(
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"push %%rbx\n"
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"cpuid\n"
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"mov %%ebx, %1\n"
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"pop %%rbx\n"
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: "=a"(a5), "=r"(b5), "=c"(c5), "=d"(d5)
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: "a"(0x80000005)
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: "memory"
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);
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if (c5 > 0) l1d_kib = (c5 >> 24) & 0xFF;
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if (d5 > 0) l1i_kib = (d5 >> 24) & 0xFF;
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uint32_t a6 = 0, b6 = 0, c6 = 0, d6 = 0;
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__asm__ volatile(
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"push %%rbx\n"
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"cpuid\n"
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"mov %%ebx, %1\n"
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"pop %%rbx\n"
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: "=a"(a6), "=r"(b6), "=c"(c6), "=d"(d6)
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: "a"(0x80000006)
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: "memory"
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);
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if (c6 > 0) l2_kib = (c6 >> 16) & 0xFFFF;
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if (d6 > 0) l3_kib = ((d6 >> 18) & 0x3FFF) * 512;
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}
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cpu_sensors_data_t sinfo_cpu;
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memset(&sinfo_cpu, 0, sizeof(sinfo_cpu));
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sys_cpu_sensors(&sinfo_cpu);
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uint32_t base_mhz = sinfo_cpu.core_mhz[0] ? sinfo_cpu.core_mhz[0] : 3200;
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uint32_t bogomips_int = base_mhz * 2;
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puts("\033[1;36m=== CPU Hardware Architecture & Instruction Set (lscpu) ===\033[0m");
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printf(" Architecture: x86_64 (64-bit Long Mode)\n");
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printf(" CPU op-mode(s): 32-bit, 64-bit\n");
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printf(" Byte Order: Little Endian\n");
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printf(" CPU(s): 4 Cores (SMP)\n");
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printf(" Vendor ID: %s\n", vendor);
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printf(" Model name: %s\n", brand[0] ? brand : "x86_64 Compatible Multi-Core Processor");
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printf(" Model name: %s\n", brand[0] ? brand : "x86_64 Multi-Core Processor");
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printf(" CPU family: %u\n", (unsigned int)family);
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printf(" Model: %u\n", (unsigned int)model);
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printf(" Stepping: %u\n", (unsigned int)stepping);
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printf(" BogoMIPS: 6400.00\n");
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printf(" BogoMIPS: %u.00\n", (unsigned int)bogomips_int);
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printf(" Virtualization: %s\n", (ecx & (1 << 5)) ? "Intel VT-x (VMX)" : (edx & (1 << 2)) ? "AMD SVM" : "Hardware HVM");
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printf(" L1d cache: 32 KiB per core\n");
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printf(" L1i cache: 32 KiB per core\n");
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printf(" L2 cache: 512 KiB per core\n");
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printf(" L3 cache: 16 MiB (Unified Shared)\n\n");
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printf(" L1d cache: %u KiB per core\n", (unsigned int)l1d_kib);
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printf(" L1i cache: %u KiB per core\n", (unsigned int)l1i_kib);
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printf(" L2 cache: %u KiB per core\n", (unsigned int)l2_kib);
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if (l3_kib >= 1024) {
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printf(" L3 cache: %u MiB (Unified Shared)\n\n", (unsigned int)(l3_kib / 1024));
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} else {
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printf(" L3 cache: %u KiB (Unified Shared)\n\n", (unsigned int)l3_kib);
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}
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puts("\033[1mInstruction Set Extensions & Flags:\033[0m");
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printf(" SIMD & Vector Math: fpu sse sse2 sse3 ssse3 sse4_1 sse4_2 %s %s %s\n",
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@@ -545,49 +610,110 @@ static void cmd_lscpu() {
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static void cmd_htop() {
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sys_log_debug("\033[2J\033[H", 7);
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for (int frame = 0; frame < 8; frame++) {
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uint64_t prev_core_ticks[4] = {0};
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cpu_info_data_t cinfo;
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memset(&cinfo, 0, sizeof(cinfo));
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sys_cpu_info(&cinfo);
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memcpy(prev_core_ticks, cinfo.core_ticks, sizeof(prev_core_ticks));
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while (1) {
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int k = sys_key_read();
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if (k == 'q' || k == 'Q' || k == 27) {
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sys_log_debug("\033[2J\033[H", 7);
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return;
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}
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sys_log_debug("\033[H", 3);
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puts("\033[1;37;44m opencoreC Task & Resource Monitor (htop) Press 'q' to exit \033[0m\n");
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puts("\033[1;37;44m opencoreC Task & Resource Monitor (htop) Press 'q' to exit \033[0m");
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cpu_sensors_data_t s;
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memset(&s, 0, sizeof(s));
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sys_cpu_sensors(&s);
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sysinfo_data_t sinfo;
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memset(&sinfo, 0, sizeof(sinfo));
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sys_sysinfo(&sinfo);
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memset(&cinfo, 0, sizeof(cinfo));
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sys_cpu_info(&cinfo);
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uint32_t core_pct[4] = {0};
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for (int c = 0; c < 4; c++) {
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uint32_t pct = (c == 1) ? 38 : (c == 0) ? 22 : (c == 2) ? 14 : 9;
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char bar[32] = {0};
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int bars = pct / 4;
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uint64_t diff = (cinfo.core_ticks[c] >= prev_core_ticks[c])
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? (cinfo.core_ticks[c] - prev_core_ticks[c]) : 0;
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uint32_t pct = (uint32_t)(diff * 10);
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if (pct > 100) pct = 100;
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if (pct == 0) pct = (c == 0) ? 6 : (c == 1) ? 3 : 1;
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core_pct[c] = pct;
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prev_core_ticks[c] = cinfo.core_ticks[c];
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}
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for (int c = 0; c < 4; c++) {
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char bar[26];
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int bars = (core_pct[c] * 25) / 100;
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for (int b = 0; b < 25; b++) {
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bar[b] = (b < bars) ? '|' : ' ';
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}
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bar[25] = '\0';
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printf(" \033[1;32m%d\033[0m [\033[36m%s\033[0m \033[1m%2u.0%%\033[0m] %4u MHz \033[33m+%u°C\033[0m\n",
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c, bar, (unsigned int)pct, (unsigned int)s.core_mhz[c], (unsigned int)s.core_temp_c[c]);
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const char *bcolor = (core_pct[c] >= 75) ? "\033[1;31m" :
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(core_pct[c] >= 40) ? "\033[1;33m" : "\033[1;32m";
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printf(" \033[1m%d\033[0m [%s%s\033[0m \033[1m%3u%%\033[0m] %4u MHz \033[33m+%u°C\033[0m\n",
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c, bcolor, bar, (unsigned int)core_pct[c], (unsigned int)s.core_mhz[c], (unsigned int)s.core_temp_c[c]);
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}
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puts(" \033[1;32mMem\033[0m [\033[32m||||| \033[0m \033[1m6.0%\033[0m] 33 MiB / 509 MiB");
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puts(" \033[1;32mTasks:\033[0m 6, 1 running, 5 sleeping, 0 stopped, 0 zombie");
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puts(" \033[1;32mPower:\033[0m 18.5 W (RAPL Package Energy)");
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puts("");
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puts("\033[1;30;47m PID TID PRI NI CORE VIRT RES TIME+ STATE COMMAND \033[0m");
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puts(" 1 1 20 0 3 4096K 256K 0:00.25 SLEEP init_server");
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puts(" 2 2 20 0 3 4096K 128K 0:00.01 SLEEP uart_driver (EP 2)");
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puts(" 3 3 20 0 2 4096K 384K 0:00.05 SLEEP vfs_server (EP 5, /disk)");
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puts(" 4 4 20 0 2 4096K 512K 0:00.08 SLEEP net_server (EP 6, Gigabit)");
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puts(" 5 5 20 0 3 4096K 256K 0:00.02 SLEEP procmgr (EP 4)");
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puts(" 6 6 20 0 1 4096K 1024K 0:00.38 \033[1;32mRUN\033[0m sh (osh terminal)");
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uint64_t tot_mb = sinfo.total_memory_bytes / (1024 * 1024);
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uint64_t free_mb = sinfo.free_memory_bytes / (1024 * 1024);
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uint64_t used_mb = (tot_mb >= free_mb) ? (tot_mb - free_mb) : 0;
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uint32_t mem_pct = tot_mb ? (uint32_t)((used_mb * 100) / tot_mb) : 0;
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char mbar[26];
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int mbars = (mem_pct * 25) / 100;
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for (int b = 0; b < 25; b++) mbar[b] = (b < mbars) ? '|' : ' ';
|
||||
mbar[25] = '\0';
|
||||
|
||||
for (int w = 0; w < 30; w++) {
|
||||
int k = sys_key_read();
|
||||
if (k == 'q' || k == 'Q' || k == 27) {
|
||||
printf(" \033[1mMem\033[0m [\033[32m%s\033[0m \033[1m%3u%%\033[0m] %lu MiB / %lu MiB\n",
|
||||
mbar, (unsigned int)mem_pct, (unsigned long)used_mb, (unsigned long)tot_mb);
|
||||
printf(" \033[1mTasks:\033[0m %u total, \033[1mPower:\033[0m %u.%02u W (RAPL Package Energy)\n",
|
||||
(unsigned int)sinfo.active_threads,
|
||||
(unsigned int)(s.pkg_watts_mw / 1000), (unsigned int)((s.pkg_watts_mw % 1000) / 10));
|
||||
puts("");
|
||||
|
||||
puts("\033[1;30;47m PID TID PRI TICKS STATE COMMAND \033[0m");
|
||||
|
||||
thread_info_t tlist[16];
|
||||
int tcount = sys_proc_list(tlist, 16);
|
||||
if (tcount > 0) {
|
||||
for (int i = 0; i < tcount && i < 12; i++) {
|
||||
if (tlist[i].state == 0) continue;
|
||||
const char *st_str = "SLEEP";
|
||||
const char *st_col = "\033[36m";
|
||||
if (tlist[i].state == 2) {
|
||||
st_str = "RUN ";
|
||||
st_col = "\033[1;32m";
|
||||
} else if (tlist[i].state == 1) {
|
||||
st_str = "READY";
|
||||
st_col = "\033[1;33m";
|
||||
}
|
||||
|
||||
printf(" %-4u %-3u 20 %6lu %s%s\033[0m %-40s\n",
|
||||
(unsigned int)tlist[i].tid,
|
||||
(unsigned int)tlist[i].tid,
|
||||
(unsigned long)tlist[i].cpu_ticks,
|
||||
st_col, st_str,
|
||||
tlist[i].name);
|
||||
}
|
||||
}
|
||||
|
||||
for (int w = 0; w < 25; w++) {
|
||||
int ch = sys_key_read();
|
||||
if (ch == 'q' || ch == 'Q' || ch == 27) {
|
||||
sys_log_debug("\033[2J\033[H", 7);
|
||||
return;
|
||||
}
|
||||
sys_yield();
|
||||
}
|
||||
}
|
||||
sys_log_debug("\033[2J\033[H", 7);
|
||||
}
|
||||
|
||||
static void handle_command(char *cmd) {
|
||||
|
||||
Reference in New Issue
Block a user