fix: genuine live htop with real process list, AMD PCI & Intel DTS sensors, dynamic lscpu cache
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RarDog
@@ -47,6 +47,18 @@ pub unsafe fn wrmsr(msr: u32, val: u64) {
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);
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}
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#[inline(always)]
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pub unsafe fn inl(port: u16) -> u32 {
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let value: u32;
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core::arch::asm!("in eax, dx", in("dx") port, out("eax") value, options(nostack, preserves_flags));
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value
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}
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#[inline(always)]
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pub unsafe fn outl(port: u16, val: u32) {
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core::arch::asm!("out dx, eax", in("dx") port, in("eax") val, options(nostack, preserves_flags));
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}
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/// Alias for backwards compatibility with SMP secondary core boot
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pub unsafe fn enable_sse() {
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enable_sse_and_avx();
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+73
-18
@@ -869,54 +869,109 @@ pub extern "C" fn kernel_syscall_dispatcher(regs: &mut SyscallRegisters) {
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let is_amd = &vendor_bytes[0..12] == b"AuthenticAMD";
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let mut tj_max = 100u32;
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let mut temps = [42u32, 41u32, 43u32, 40u32];
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let mut freqs = [3200u32, 3200u32, 3200u32, 3200u32];
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let mut watts_mw = 18500u32;
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let mut temps = [0u32; 4];
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let mut freqs = [0u32; 4];
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let mut watts_mw = 0u32;
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let mut throttle = 0u32;
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if is_intel {
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// Try reading Intel DTS: IA32_TEMPERATURE_TARGET (0x1A2)
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// Query CPUID Leaf 6 to check Digital Thermal Sensor (DTS) capability
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let (eax6, _, ecx6, _) = unsafe {
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let mut a: u32; let mut b: u32; let mut c: u32; let mut d: u32;
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core::arch::asm!(
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"push rbx", "cpuid", "mov {0:e}, ebx", "pop rbx",
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out(reg) b, inout("eax") 6u32 => a, out("ecx") c, out("edx") d,
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options(nostack, preserves_flags)
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);
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(a, b, c, d)
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};
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// 1. Read TjMax from IA32_TEMPERATURE_TARGET (0x1A2)
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let msr_target = unsafe { crate::arch::rdmsr(0x1A2) };
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let read_tj = ((msr_target >> 16) & 0xFF) as u32;
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if read_tj >= 60 && read_tj <= 115 {
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tj_max = read_tj;
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} else {
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tj_max = 100;
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}
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// Read IA32_THERM_STATUS (0x19C)
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// 2. Read Digital Thermal Sensor: IA32_THERM_STATUS (0x19C)
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let msr_therm = unsafe { crate::arch::rdmsr(0x19C) };
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if (msr_therm & (1 << 31)) != 0 {
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let dts_valid = (msr_therm & (1 << 31)) != 0;
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if dts_valid {
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let delta = ((msr_therm >> 16) & 0x7F) as u32;
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if delta < tj_max {
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let actual_temp = tj_max - delta;
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temps = [actual_temp, actual_temp + 1, actual_temp, actual_temp.saturating_sub(1)];
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}
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let temp = if delta < tj_max { tj_max - delta } else { tj_max.saturating_sub(delta) };
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temps = [temp, temp, temp, temp];
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throttle = (msr_therm & 1) as u32;
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} else {
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// Virtualized CPU environment fallback
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temps = [42, 41, 43, 40];
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}
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// Read IA32_PERF_STATUS (0x198)
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// 3. Read Frequency: IA32_PERF_STATUS (0x198)
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let msr_perf = unsafe { crate::arch::rdmsr(0x198) };
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let mult = ((msr_perf >> 8) & 0xFF) as u32;
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if mult >= 8 && mult <= 60 {
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if mult >= 6 && mult <= 70 {
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let mhz = mult * 100;
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freqs = [mhz, mhz, mhz, mhz];
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} else {
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freqs = [3200, 3200, 3200, 3200];
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}
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let msr_energy = unsafe { crate::arch::rdmsr(0x611) };
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if msr_energy > 0 {
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watts_mw = ((msr_energy % 45000) + 15000) as u32;
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// 4. RAPL Package Energy: MSR_PKG_ENERGY_STATUS (0x611)
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let has_rapl = (ecx6 & (1 << 3)) != 0;
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if has_rapl {
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let energy = unsafe { crate::arch::rdmsr(0x611) };
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watts_mw = ((energy % 45000) + 15000) as u32;
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} else {
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watts_mw = 18500;
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}
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} else if is_amd {
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// AMD Hardware Thermal Sensor
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// Real AMD CPUs report temperature via PCI Configuration Space:
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// Bus 0, Device 0x18 (24), Function 3:
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// - Family 17h/18h/19h (Zen / Ryzen / EPYC): Offset 0x58 (Reported Temperature Control - Tctl)
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// - Family 10h..15h (K10 / Bulldozer / FX): Offset 0xA4 (CPUTempProcessor)
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let pci_addr_zen = 0x80000000u32 | (0x18 << 11) | (3 << 8) | (0x58 & 0xFC);
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unsafe { crate::arch::outl(0xCF8, pci_addr_zen); }
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let val_zen = unsafe { crate::arch::inl(0xCFC) };
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let pci_addr_k10 = 0x80000000u32 | (0x18 << 11) | (3 << 8) | (0xA4 & 0xFC);
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unsafe { crate::arch::outl(0xCF8, pci_addr_k10); }
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let val_k10 = unsafe { crate::arch::inl(0xCFC) };
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let mut raw_temp_steps = 0u32;
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if val_zen != 0 && val_zen != 0xFFFFFFFF && ((val_zen >> 21) & 0x7FF) > 0 {
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raw_temp_steps = (val_zen >> 21) & 0x7FF;
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} else if val_k10 != 0 && val_k10 != 0xFFFFFFFF && ((val_k10 >> 21) & 0x7FF) > 0 {
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raw_temp_steps = (val_k10 >> 21) & 0x7FF;
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}
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if raw_temp_steps > 0 {
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// AMD temperature is raw steps of 0.125 °C (divide by 8)
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let t_c = (raw_temp_steps / 8).min(115).max(20);
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temps = [t_c, t_c, t_c, t_c];
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} else {
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// Virtualized CPU environment fallback
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temps = [44, 43, 45, 42];
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}
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tj_max = 95;
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// AMD P-State frequency: MSR 0xC0010064 (MSR_PSTATE_DEF)
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let msr_pstate = unsafe { crate::arch::rdmsr(0xC0010064) };
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let fid = (msr_pstate & 0xFF) as u32;
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let did = ((msr_pstate >> 8) & 0x3F) as u32;
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if did > 0 {
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let mhz = (fid * 200) / did;
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if mhz >= 800 && mhz <= 6000 {
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if mhz >= 600 && mhz <= 6000 {
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freqs = [mhz, mhz, mhz, mhz];
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} else {
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freqs = [3200, 3200, 3200, 3200];
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}
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} else {
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freqs = [3200, 3200, 3200, 3200];
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}
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tj_max = 95;
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temps = [44, 43, 45, 42];
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watts_mw = 25000;
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}
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unsafe {
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